In general, a high withstand voltage semiconductor device (a power device) to which high voltage is applied is employed in the field of power electronics.
A vertical structure capable of easily feeding high current and capable of easily ensuring high withstand voltage and low on-resistance is known as the structure of the power device (for example, Patent Document 1).
A power device of the vertical structure includes an n+-type substrate, an n−-type epitaxial layer stacked on the substrate, p-type body regions plurally formed on a surface layer portion of the epitaxial layer at an interval, and an n+-type source region formed on a surface layer portion of each body region, for example. A gate insulating film is formed to extend between adjacent body regions, and a gate electrode is formed on the gate insulating film. The gate electrode is opposed to each body region through the gate insulating film. A source electrode is electrically connected to the source region. On the other hand, a drain electrode is formed on the back surface of the substrate. Thus, the power device of the vertical structure in which the source electrode and the drain electrode are arranged in a vertical direction perpendicular to the major surface of the substrate is constituted.
Voltage of not less than a threshold is applied to the gate electrode in a state applying voltage between the source electrode and the drain electrode (between a source and a drain), whereby channels are formed in the vicinity of interfaces between the body regions and the gate insulating film due to an electric field from the gate electrode. Thus, current flows between the source electrode and the drain electrode, and the power device enters an ON-state.